Low-power vlsi architectures for finite field applications

This thesis focuses on the design of VLSI architectures for fundamental finite field arithmetic operations and their applications including Reed-Solomon error-control codecs and elliptic-curve public-key cryptography systems that are extensively used to achieve secure and reliable transmission and storage in digital communication and recording systems. The basic concepts of finite fields, and the algorithms for RS encoding and decoding, and elliptic curve cryptography are well understood. Previous research in this area addressed design of low-complexity and high-speed dedicated (application-specific) VLSI architectures to cut the cost and meet real-time speed requirements. The work presented in this thesis carries on this design trend for high-speed and low-complexity; moreover, it emphasizes the design of low-energy programmable VLSI architectures for finite field applications. At the arithmetic units level, various architectures are presented to perform finite field multiplication more efficiently. Low-area and low-latency programmable semi-systolic parallel multiplier, squarer, and exponentiator are proposed. Design of low-complexity dedicated finite field multipliers and dual-basis divider are also presented in this thesis. Moreover, a novel digit-serial multiplication scheme is presented, which has much smaller energy-latency product than the digit-serial multiplier obtained by folding the parallel multiplier. At the system level, hardware/software codesign is considered for the design of programmable Reed-Solomon codecs and energy-scalable elliptic curve encryption processor. These systems are to be implemented as a combination of hardware and software in application-specific DSP processors with specially designed programmable datapath and dedicated and optimized software to reduce total energy consumption. The cross-talk between hardware and software design ensures that the resulting system best exploited the trade-off between programmability and performance optimization. Energy reduction in RS codecs is achieved by using a novel datapath architecture with low-energy finite field multiplication units; and by reducing the total number of energy-consuming computations through use of a modified RS decoding algorithm and effective software coding. The energy-scalable elliptic curve encryption processor is based on a composite finite field representation, which makes it possible to reduce the total energy consumption by sacrificing some security for low-priority data while adequately protecting the important information.