Optimization of Buffer Stages in Bipolar VLSI Systems

This work deals with the optimization of the following buffer stages used in ECL and Cascode ECL VLSI systems: a) the level shifters (including the pure emitter follower) and b) the Darlington configuration. Analytical delay expressions for all these buffer stages have been extracted considering high speed operation. In addition, the optimum bias current(s) achieving the minimum power-delay product have been determined. The same delay expressions apply also to BiCMOS buffers. The expressions extracted combine simplicity and accuracy leading to a fast optimization procedure.

[1]  Sidney Soclof.  Analog integrated circuits , 1985 .

[2]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  P. M. Solomon,et al.  Bipolar transistor design for optimized power-delay logic circuits , 1979 .

[4]  W. Fang.  Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits , 1990 .

[5]  G. P. Rosseel,et al.  Influence of device parameters on the switching speed of BiCMOS buffers , 1989 .

[6]  C. T. Kirk,et al.  A theory of transistor cutoff frequency (fT) falloff at high current densities , 1962, IRE Transactions on Electron Devices.

[7]  Catherine Mallardeau,et al.  A 10 K-gate 950 MHz CML demonstrator circuit made with a 1- mu m trench-isolated bipolar silicon technology , 1989 .

[8]  Sung-Mo Kang,et al.  An accurate analytical delay model for BiCMOS driver circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  B.-Y. Hwang,et al.  An improved high-performance logic gate using series diode and resistor loads for ECL/CML applications , 1989 .

[10]  Robert Mertens,et al.  An analytical model for the determination of the transient response of CML and ECL gates , 1990 .

[11]  A. Brunnschweiler,et al.  A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes , 1988 .

[12]  Minoru Fujishima,et al.  Evaluation of delay-time degradation of low-voltage BiCMOS based on a novel analytical delay-time modeling , 1991 .

[13]  B. Hoefflinger,et al.  Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects , 1986, IEEE Transactions on Electron Devices.