Conceptual Improvisation on Low Power Mitigation for Domino Logic Systems using CHSK Domino Logic

Background/Objectives: In VLSI technology, the design provide low-power static random access to various applications and also performs with less energy and design implementation reduces the burden and also manages the delay. Methods/Statistical Analysis: The mixed domino high-speed circuit was designed with a wide domino logic circuit with a multiplexer. We propose a wide domino logic circuit of CHSK domino logic circuits to improve the performance of the parameters like Power, Delay, Unity Noise Gain, Power Delay Product and Robustness. Findings: The technique used in domino logic circuit designs and usage of higher order multiplexer of a modular design is presented and implemented by constructing a multiplexer. Simulation is done using Cadence CMOS process using Virtuoso tool. Application/Improvements: The proposed circuit improves unity noise gain, delay and power along with better performance as compared to Conditional Keeper and High Speed domino logic circuit of existing domino logic systems.