论文信息 - A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry - 字舞流文

A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry

Fujiwara Hidehiro | Nii Koji | Yabuuchi Makoto | Tsukamoto Yasumasa | Ishii Yuichiro | Matsumura Tetsuya | Matsuda Yoshio