Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

The embedded flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. First, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15 mum eFlash technology. Next, we propose a study of resistive defect injections in eFlash memories to show the relevance of the proposed simulation model. At the end of the paper, a table summarizes the functional fault models for different resistive defect configurations and experimental set-ups. According to these first results and with additional analysis of actual defects presented in [1] we are then able to enhance existing test solutions for eFlash testing.

[1]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[2]  Kewal K. Saluja,et al.  Flash memory disturbances: modeling and test , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[3]  Tetsuo Endoh,et al.  Reliability issues of flash memory cells , 1993, Proc. IEEE.

[4]  Approved June,et al.  IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays , 1991 .

[5]  J. F. Dickson,et al.  On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique , 1976 .

[6]  Kiyoo Itoh,et al.  Vlsi Memory Chip Design , 2006 .

[7]  Arnaud Virazel,et al.  An overview of failure mechanisms in embedded flash memories , 2006, 24th IEEE VLSI Test Symposium.

[8]  Kewal K. Saluja,et al.  Simulating program disturb faults in flash memories using SPICE compatible electrical model , 2003 .

[9]  Yea-Ling Horng,et al.  A realistic fault model for flash memories , 2000, Proceedings of the Ninth Asian Test Symposium.

[10]  Jen-Chieh Yeh,et al.  RAMSES-FT: a fault simulator for flash memory testing and diagnostics , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[11]  Piero Olivo,et al.  Flash memory cells-an overview , 1997, Proc. IEEE.

[12]  Jean Michel Portal,et al.  Floating-gate EEPROM cell model based on MOS model 9 , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).