Reconfigurable systolic architectures for hashing

The authors develop a novel technique in which concepts of both bucketing and open addressing schemes are modified in such a manner that they can be suitable for VLSI/WSI implementation, namely, dynamically reconfigurable hash tables. In this method, finite storage is allocated for each bucket. Instead of searching the entire table or a part of the table for an empty storage place, the overflowing synonyms are inserted into the successor's bucket (next to the home bucket). If the successor's bucket overflows, the same technique is repeated until the table is stable. The host bucket takes care of all the relative operations for its guest items. As soon as an empty place arises in the original bucket, the host bucket returns the guest element to the original bucket: in essence, dynamically variable capacity buckets have been created. These buckets are designed using systolic arrays.<<ETX>>