Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

[1]  Tao Yang,et al.  A Novel Capacitorless 1T DRAM with Embedded Oxide Layer , 2022, Micromachines.

[2]  K. Sakui,et al.  Dynamic Flash Memory with fast block refresh feature using double storage gates and one select gate , 2022, Memories - Materials, Devices, Circuits and Systems.

[3]  Chih-Yuan Lu,et al.  First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures , 2022, 2022 IEEE International Reliability Physics Symposium (IRPS).

[4]  Jang-Rae Kim,et al.  A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process , 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

[5]  K. Sakui,et al.  Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT) , 2021, 2021 IEEE International Memory Workshop (IMW).

[6]  T. Ohsawa,et al.  Floating Body RAM Technology and its Scalability to 32nm Node and Beyond , 2006, 2006 International Electron Devices Meeting.

[7]  M.J. Declercq,et al.  Capacitorless 1T DRAM sensing scheme with automatic reference generation , 2006, IEEE Journal of Solid-State Circuits.

[8]  Takashi Ohsawa,et al.  An 18.5ns 128MB SOI DRAM with a floating body cell , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[9]  Akihiro Nitayama,et al.  Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[10]  S. Okhonin,et al.  A new block refresh concept for SOI floating body memories , 2003, 2003 IEEE International Conference on SOI.

[11]  Jean-Michel Sallese,et al.  A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[12]  S. Okhonin,et al.  A capacitor-less 1T-DRAM cell , 2002, IEEE Electron Device Letters.

[13]  T. Ohsawa,et al.  Memory design using one-transistor gain cell on SOI , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[14]  Jean-Michel Sallese,et al.  A SOI capacitor-less 1T-DRAM concept , 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

[15]  Fumio Horiguchi,et al.  High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs , 1988, Technical Digest., International Electron Devices Meeting.

[16]  K. Ohuchi,et al.  A new static memory cell based on reverse base current (RBC) effect of bipolar transistor , 1988, Technical Digest., International Electron Devices Meeting.