A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption

Presented is the first continuous-time (CT) digital infinite impulse response (IIR) filter working on signal-derived timing in lieu of a clock. We introduce a novel design method which enables the design of high-order IIR filters using only two tap delays. An event-grouping technique is also introduced to prevent parasitic oscillations in the presence of tap delay mismatches. The 1.2-V, 65-nm CMOS prototype implements a sixth-order IIR filter, with a maximum input rate of 20 Msample/s and a stop-band rejection of more than 80 dB. Without using any power-down circuitry, the chip’s power consumption tracks the input activity in a fully agile manner, and varies by more than <inline-formula> <tex-math notation="LaTeX">$50\times $ </tex-math></inline-formula>, from 0.04 to 2.32 mW. The filter achieves an figure of merit (FoM) which competes with that of discrete-time (DT) filters, while avoiding the use of a clock and an antialiasing filter. Compared to prior art in CT digital signal processings, the prototype achieves 45-dB improvement in stop-band rejection and 9<inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> smaller delay line area. For the first time, the filtered CT digital signal is converted to synchronous mode at the end of signal chain, allowing integration with DT digital systems.