DW-LOCOS: a convenient VLSI isolation technique
暂无分享,去创建一个
[1] J. P. Krusius,et al. Field Oxide Thinning in Poly Buffer LOCOS Isolation with Active Area Spacings to 0.1 μm , 1990 .
[2] K. Sakuma,et al. A New Self‐Aligned Planar Oxidation Technology , 1987 .
[3] H. Higuchi,et al. Evaluation of Dislocation Generation at Si3 N 4 Film Edges on Silicon Substrates by Selective Oxidation , 1981 .
[4] J. A. Appels,et al. Formation of Silicon Nitride at a Si ‐ SiO2 Interface during Local Oxidation of Silicon and during Heat‐Treatment of Oxidized Silicon in NH 3 Gas , 1976 .
[5] Simon Deleonibus,et al. Exploration of LOCOS-type isolation limit using SUPERSILO isolation by rapid thermal nitridation of silicon , 1993 .
[6] A New Preferential Etch for Defects in Silicon Crystals , 1977 .
[7] S. Shinozaki,et al. Oxidation rate reduction in the submicrometer LOCOS process , 1987, IEEE Transactions on Electron Devices.
[8] R. J. Saia,et al. LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology , 1989 .
[9] Kuang Yi Chiu,et al. A bird's beak free local oxidation technology feasible for VLSI circuits fabrication , 1982 .
[10] J. Gonchond,et al. Physical and electrical characterization of a SILO isolation structure , 1985, IEEE Transactions on Electron Devices.
[11] R. Guldi,et al. Characterization of Poly‐Buffered LOCOS in Manufacturing Environment , 1989 .
[12] A. S. Grove,et al. General Relationship for the Thermal Oxidation of Silicon , 1965 .
[13] T. A. Shankoff,et al. Bird's Beak Configuration and Elimination of Gate Oxide Thinning Produced during Selective Oxidation , 1980 .