A 65-nm 8T Sub-threshold SRAM Employing Sense-amplifier Redundancy

Deeply scaled technologies promise greater efficiency for digital circuits. Unfortunately, random device variations compromise the functionality of large SRAM arrays, which traditionally rely on ratioed bit-cell topologies to achieve the highest density. By virtue of greatly reduced leakage and access energy, sub-threshold SRAMs tremendously lower the total system power but require new bit-cell topologies and peripheral assists to manage variation and read-current degradation [1]. This work demonstrates a 256kb SRAM in 65-nm CMOS that uses the bit-cell shown in Figure 1 [2]. The buffered read eliminates the read static noise margin limitation [3]; peripheral footer circuitry eliminates read data signal degradation due to bit-line leakage; peripheral supply drivers weaken the accessed storage cells to enforce the relative device strengths required for write-ability; and sense-amplifier redundancy provides a favorable trade-off between the offset and the area of the sensing network. These techniques are applied in the prototype test-chip shown in Figure 2. The test-chip integrates 256kb-in-8, 256-row-by-128-column blocks. Test results show that the design achieves full read and write functionality to 350mV, where the leakage power savings are over 20x compared to a 6T SRAM at 1V and over 3x compared to a 6T SRAM operating at its projected lowest voltage. Additionally, sense-amplifier redundancy reduces the probability of error from offsets by a factor of 5 for a given area constraint.