Impact of Bias Temperature Instability on Soft Error Susceptibility

In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime.

[1]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.

[2]  Janak H. Patel,et al.  A logic-level model for /spl alpha/-particle hits in CMOS circuits , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[3]  V. Huard,et al.  Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS transistors , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[4]  Yu Cao,et al.  An efficient method to identify critical gates under circuit aging , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[5]  Cecilia Metra,et al.  Transient Fault and Soft Error On-die Monitoring Scheme , 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

[6]  G. Groeseneken,et al.  From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[7]  Cecilia Metra,et al.  Model for Transient Fault Susceptibility of Combinational Circuits , 2004, J. Electron. Test..

[8]  Muhammad Ashraful Alam,et al.  A comprehensive model of PMOS NBTI degradation , 2005, Microelectron. Reliab..

[9]  Cecilia Metra,et al.  Low Cost NBTI Degradation Detection and Masking Approaches , 2013, IEEE Transactions on Computers.

[10]  Thomas A. DeMassa,et al.  Digital Integrated Circuits , 1985, 1985 IEEE GaAs IC Symposium Technical Digest.

[11]  Abhijit Chatterjee,et al.  On transistor level gate sizing for increased robustness to transient faults , 2005, 11th IEEE International On-Line Testing Symposium.

[12]  John Keane,et al.  An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Bo Yang,et al.  Optimized Circuit Failure Prediction for Aging: Practicality and Promise , 2008, 2008 IEEE International Test Conference.

[14]  P.H. Eaton,et al.  SEU and SET Modeling and Mitigation in Deep Submicron Technologies , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[15]  Kartik Mohanram,et al.  Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Cecilia Metra,et al.  Impact of Aging Phenomena on Soft Error Susceptibility , 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

[17]  Narayanan Vijaykrishnan,et al.  Variation Impact on SER of Combinational Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[18]  Federico Faccio,et al.  Impact of NBTI Aging on the Single-Event Upset of SRAM Cells , 2010, IEEE Transactions on Nuclear Science.

[19]  Abhijit Chatterjee,et al.  Accurate Linear Model for SET Critical Charge Estimation , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Daniele Rossi,et al.  Low Cost NBTI Degradation Detection & Masking Approaches , 2011 .

[21]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[22]  Ming Zhang,et al.  On the Scalability of Redundancy based SER Mitigation Schemes , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

[23]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[25]  Cecilia Metra,et al.  High-Performance Robust Latches , 2010, IEEE Transactions on Computers.

[26]  Hamid Mahmoodi,et al.  Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology , 2011, 2011 12th International Symposium on Quality Electronic Design.

[27]  R.V. Joshi,et al.  The Impact of Aging Effects and Manufacturing Variation on SRAM Soft-Error Rate , 2008, IEEE Transactions on Device and Materials Reliability.

[28]  Masanori Hashimoto,et al.  Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement , 2013, IEEE Transactions on Nuclear Science.

[29]  Adta.  home page (online) , 2004 .

[30]  M. Omaña,et al.  Self-checking monitor for NBTI due degradation , 2010, 2010 IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW).

[31]  Francky Catthoor,et al.  BTI impact on logical gates in nano-scale CMOS technology , 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[32]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .