VLSI architecture for digital picture comparison

The authors propose a VLSI architecture consisting of m*n processing elements with extensive parallel and pipelining computational capabilities. The worst-case time complexity is reduced to O(max(m, n)), which is a significant improvement over the uniprocessor approach. The algorithm partition problem, an important issue in VLSI design, and the verification of the proposed architecture are also studied. A series of experiments conducted to verify the proposed algorithms is described. >