Modeling the effects of systematic process variation of circuit performance

As technology scales, understanding semiconductor manufacturing variation becomes essential to effectively design high performance circuits. Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise. Conventional circuit techniques typically represent the interconnect and device parameter variations as random variables. However, recent studies have shown that strong spatial pattern dependencies exist, especially when considering interconnect variation in chemical mechanical polishing (CMP) processes. Therefore, the total variation can be separated into systematic and random components, where a significant portion of the variation can be modeled based on layout characteristics. Modeling the systematic components of different variation sources and implementing these effects in circuit simulation are key to reduce design uncertainty and maximize circuit performance. This thesis presents a methodology to incorporate systematic pattern dependent interconnect and device variation models for use with circuit extraction and simulation tools. The methodology is applicable to variation impact assessment as well as variation reduction during circuit design. Systematic models are implemented within a computer aided design (CAD) tool environment to enable automated analysis since the impact of variation is a function of circuit type, performance metric, type of technology, and type of variation source under consideration. The methodology is then applied to study the effects of different variation sources on high performance microprocessor circuit designs for the various performance metrics. The impact of variation is also projected as technology is scaled to the 50 nm generation. Our results indicate that design margin can be tightened significantly if systematic variation models are used for circuit simulation, especially with technology scaling. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

[1]  P. Zarkesh-Ha,et al.  Characterization and modeling of clock skew with process variations , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[2]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[3]  Lars W. Liebmann,et al.  Understanding across-chip line-width variation: the first step toward optical proximity correction , 1997, Advanced Lithography.

[4]  D. S. Wills,et al.  Minimum repeater count, size, and energy dissipation for gigascale integration (GSI) interconnects , 1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).

[5]  Dennis Sylvester,et al.  On-chip cross talk noise model for deep-submicrometer ULSI interconnect , 1998 .

[6]  Sani R. Nassif,et al.  Models of process variations in device and interconnect , 2000 .

[7]  Duane S. Boning,et al.  A CLOSED-FORM ANALYTIC MODEL FOR ILD THICKNESS VARIATION IN CMP PROCESSES , 1997 .

[8]  Andrea Neviani,et al.  Analysis of the impact of intra-die variance on clock skew , 1999, 1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391).

[9]  Duane S. Boning,et al.  PATTERN AND PROCESS DEPENDENCIES IN COPPER DAMASCENE CHEMICAL MECHANICAL POLISHING PROCESSES , 1998 .

[10]  R. Vallishayee,et al.  On the impact of dishing in metal CMP processes on circuit performance , 1998, IWSM. 1998 3rd International Workshop on Statistical Metrology (Cat. No.98EX113).

[11]  Duane S. Boning,et al.  Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes , 1995, Proceedings of International Electron Devices Meeting.

[12]  S. Nassif,et al.  Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[13]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[14]  Ying Liu,et al.  Model order-reduction of RC(L) interconnect including variational analysis , 1999, DAC '99.

[15]  Sani R. Nassif,et al.  A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance , 2000, Proceedings 37th Design Automation Conference.

[16]  Norman Chang,et al.  Fast generation of statistically-based worst-case modeling of on-chip interconnect , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[17]  James C. Chen,et al.  A statistical performance simulation methodology for VLSI circuits , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[18]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[19]  Pei-yang Yan,et al.  Mask CD control requirement at 0.18-μm design rules for 193-nm lithography , 1997, Advanced Lithography.

[20]  D. Bartelink.  Statistical metrology: At the root of manufacturing control , 1994 .

[21]  Duane S. Boning,et al.  Analysis and decomposition of spatial variation in integrated circuit processes and devices , 1997 .

[22]  Sani R. Nassif.  Design for Variability in DSM Technologies , 2000 .

[23]  Takayasu Sakurai,et al.  Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .

[24]  Duane S. Boning,et al.  Simulating the impact of pattern-dependent poly-CD variation on circuit performance , 1998 .

[25]  Lei He,et al.  An efficient inductance modeling for on-chip interconnects , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[26]  Sriram Srinivasan,et al.  Advanced Perl Programming , 1997 .

[27]  Costas J. Spanos,et al.  Circuit sensitivity to interconnect variation , 1998 .

[28]  Duane S. Boning,et al.  USING SMART DUMMY FILL AND SELECTIVE REVERSE ETCHBACK FOR PATTERN DENSITY EQUALIZATION , 2000 .

[29]  Sani R. Nassif,et al.  Modeling and forecasting of manufacturing variations , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[30]  Duane S. Boning,et al.  Statistical metrology for interlevel dielectric thickness variation , 1994, Advanced Lithography.

[31]  Y. Hayashi,et al.  Interconnect design strategy: structures, repeaters and materials toward 0.1 /spl mu/m ULSIs with a giga-hertz clock operation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[32]  Duane S. Boning,et al.  Assessing and characterizing inter-and intra-die variation using a statistical metrology framework: A CMP case study , 1999 .

[33]  C. K. Chow.  Projection of circuit performance distributions by multivariate statistics , 1989 .

[34]  D. Boning,et al.  A MATHEMATICAL MODEL OF PATTERN DEPENDENCIES IN Cu CMP PROCESSES , 1999 .

[35]  Anirudh Devgan,et al.  Efficient coupled noise estimation for on-chip interconnects , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[36]  Mattan Kamon,et al.  FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.

[37]  B. Flachs,et al.  A 1 GHz single-issue 64 b PowerPC processor , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[38]  Yuri Granik,et al.  Efficient full-chip yield analysis methodology for OPC-corrected VLSI designs , 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

[39]  Costas J. Spanos,et al.  Circuit performance variability decomposition , 1999, 1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391).

[40]  Ronald J. Gutmann,et al.  Chemical Mechanical Planarization of Microelectronic Materials , 1997 .

[41]  T. Sakurai,et al.  Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.

[42]  Dennis Okumu Ouma,et al.  Modeling of chemical mechanical polishing for dielectric planarization , 1998 .

[43]  P. Zarkesh-Ha,et al.  Optimum chip clock distribution networks , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[44]  Jacob K. White,et al.  FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[45]  Charles J. Alpert,et al.  Buffer insertion for noise and delay optimization , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[46]  D. Boning,et al.  Technology scaling impact of variation on clock skew and interconnect delay , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[47]  Anantha Chandrakasan,et al.  Models of Process Variations in Device and Interconnect , 2001 .

[48]  O. Takahashi,et al.  A 1.0 GHz single-issue 64 b powerPC integer processor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[49]  P. Yang,et al.  Multilevel metal capacitance models for CAD design synthesis systems , 1992, IEEE Electron Device Letters.

[50]  D. Boning,et al.  The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes , 1998 .

[51]  O. S. Nakagawa,et al.  Circuit impact and skew-corner analysis of stochastic process variation in global interconnect , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[52]  Eby G. Friedman,et al.  Peak crosstalk noise estimation in CMOS VLSI circuits , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[53]  James D. Meindl,et al.  Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks , 2000 .

[54]  Yamashita,et al.  Interconnect Scaling Scenario Using A Chip Level Interconnect Model , 1997, 1997 Symposium on VLSI Technology.

[55]  V. K. De,et al.  Prospects of gigascale integration (GSI) beyond 2003 , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[56]  Dennis Sylvester,et al.  Modeling the impact of back-end process variation on circuit performance , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[57]  D.S. Boning,et al.  A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[58]  Duane S. Boning,et al.  Statistical metrology: understanding spatial variation in semiconductor manufacturing , 1996, Advanced Lithography.

[59]  D. Boning,et al.  An integrated characterization and modeling methodology for CMP dielectric planarization , 1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).

[60]  Roger Fabian W. Pease,et al.  Exploiting structure in fast aerial image computation for integrated circuit patterns , 1997 .

[61]  Duane S. Boning,et al.  MULTI-LEVEL PATTERN EFFECTS IN COPPER CMP , 1999 .

[62]  James D. Meindl,et al.  Optimal repeater insertion for n-tier multilevel interconnect architectures , 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).