A placement driven methodology for high-level synthesis of sub-micron ASIC's

This paper proposes a novel methodology for automated data-path synthesis of deep submicron Application Specific Integrated Circuits (ASICs). In contrast to other approaches, we formulate interconnect area/delay optimizations as high-level synthesis transformations and use them during the synthesis to minimize impact of wiring on circuit characteristics. Experiments with 0.5 /spl mu/m and 0.25 /spl mu/m ASIC implementations of the DCT algorithm show that such formulation jointly with performance-driven floorplanning and "on-fly" module generation provides significant wiring delay reduction.