Notice of Violation of IEEE Publication PrinciplesA 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation

This paper presents a multigigahertz active clock deskewing architecture that uses analog phase interpolation to replace the area-consuming capacitively controlled delay lines used in regional clock deskewing delay-locked loops. It provides a small phase step that is uniform and process-independent over the entire 2/spl pi/ phase deskew range, which reduces the intra-die clock skew. The phase interpolators have virtually zero latency, which leads to a very fast clock deskewing process and allows for the tracking of fast dynamic variations. A bandgap referencing technique was used to provide a tracking mechanism between the phase-locked loop (PLL) time constants to achieve a process-independent PLL damping factor and pole-zero separation. Both feedback and input divider modulus independence of the damping factor was achieved through a combined current and capacitor switching architecture, that provides an optimal compromise between area, power, and spurs. A reset-generation charge-pump architecture was introduced to minimize the dead-zone avoidance pulse width in order to improve the PLL jitter and reference spurs performance. The power supply partitioning exploits the dual gate oxide transistors offered by the current deep-submicron CMOS technologies. The biasing scheme is comprised of a 1.5-V supply for the ring oscillator and digital circuitry for speed considerations, while the analog front-end is biased from a 2.5-V supply to ensure more voltage headroom as required by low-gain oscillators and low-noise loop filters.