To reduce the cycle time and the cost of the design of ESD tolerant over-voltage I/O cells, a methodology for pre-silicon ESD protection optimisation is described, based on Technology Computer Aided Design (TCAD) (device level) and compact (circuit level) simulation studies. Using this methodology, first time right ESD tolerant over-voltage I/O cells were designed in a silicided 0.25 μm CMOS dual gate-oxide process. The methodology consists in a precise TCAD process calibration, a cascoded snapback NMOS compact model definition valid under ESD conditions, a model parameter extraction based on TCAD data and, finally, circuit level optimisation of the I/O protection circuits. Very good agreement was achieved between the simulated pre-silicon characteristics and the experimental behaviour of the I/O protection circuits.