论文信息 - Design of PLL-Based Synchronous PWM Oscillator in Class-D Power Amplifier

Design of PLL-Based Synchronous PWM Oscillator in Class-D Power Amplifier

To minimize the effect of cross talk in monolithic stereo class D power amplifier, one improved scheme in stereo application with dual-chips is presented. Pulse Width Modulation (PWM) in master and salve chip should be synchronized each other for decreasing distortion, so a Phase Locked Loop (PLL) -based synchronous oscillator is designed in class-D power amplifier chip. When power supply is 5.5V, input frequency is 1KHz and output power is 3.7W in 4 Ohm load, the Total Harmonic Noise (THD) of amplifier is less than 1% and efficiency is about 90%. The class-D amplifier quiescent current is 1.9mA and shutdown quiescent current is 0.5μA.

Fei Zhao | Yong Xu | Yu Guan | Yongbin Xu

[1] B. Zhang,et al. A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-μm CMOS , 2003, IEEE J. Solid State Circuits.

[2] Cao Zhengxin,et al. A New Structure for a CMOS Audio Power AMP with Extremely Low THD and Low Power Consumption , 2006 .

[3] Yang Yintang. The Design of a High Efficiency 2.1 Channel Class-D Audio Power Amplifier , 2008 .

[4] O. McCarthy,et al. A 20-W stereo class-D audio output power stage in 0.6-/spl mu/m BCDMOS technology , 2004, IEEE Journal of Solid-State Circuits.

[5] Enrico Dallago,et al. PWM Power Audio Amplifier With Voltage/Current Mixed Feedback for High-Efficiency Speakers , 2007, IEEE Transactions on Industrial Electronics.

[6] M. Berkhout,et al. An integrated 200W class D audio amplifier , 2003, Proceedings of the 28th European Solid-State Circuits Conference.