VLSI configurable delay commutator for a pipeline split radix FFT architecture

This paper presents a full custom one-bit slice delay commutator for a pipeline split radix FFT (SRFFT) architecture, implemented using the true single-phase-clock (TSPC) circuit technique and a 1.0-/spl mu/m CMOS technology. This circuit can be configured or all intermediate SRFFT computation levels for transforms of lengths up to N=2048, where N is power of two. The circuit has been tested up to 200 MHz, having a power consumption of 1.1 W at 5 V of power supply.

[1]  Bevan M. Baas,et al.  A low-power, high-performance, 1024-point FFT processor , 1999, IEEE J. Solid State Circuits.

[2]  Soheil I. Sayegh,et al.  A pipeline processor for mixed-size FFTs , 1992, IEEE Trans. Signal Process..

[3]  Dinesh Somasekhar,et al.  A 230 MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking , 1993, The Sixth International Conference on VLSI Design.

[4]  E.E. Swartzlander,et al.  A radix 4 delay commutator for fast Fourier transform processor implementation , 1984, IEEE Journal of Solid-State Circuits.

[5]  C. Sidney Burrus,et al.  On computing the split-radix FFT , 1986, IEEE Trans. Acoust. Speech Signal Process..

[6]  J. A. Michell,et al.  Fully pipelined TSPC barrel shifter for high-speed applications , 1995 .

[7]  Tad A. Kwasniewski,et al.  A chip set for pipeline and parallel pipeline FFT architectures , 1994, J. VLSI Signal Process..

[8]  John V. McCanny,et al.  A 64-point Fourier transform chip for video motion compensation using phase correlation , 1996, IEEE J. Solid State Circuits.

[9]  C. Joanblanq,et al.  A fast single-chip implementation of 8192 complex point FFT , 1995 .

[10]  Pierre Duhamel,et al.  Implementation of "Split-radix" FFT algorithms for complex, real, and real-symmetric data , 1986, IEEE Trans. Acoust. Speech Signal Process..

[11]  Mark A. Richards.  On hardware implementation of the split-radix FFT , 1988, IEEE Trans. Acoust. Speech Signal Process..

[12]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[13]  E. V. Jones,et al.  A pipelined FFT processor for word-sequential data , 1989, IEEE Trans. Acoust. Speech Signal Process..

[14]  P. Duhamel,et al.  `Split radix' FFT algorithm , 1984 .

[15]  G. A. Jullien,et al.  High Performance Arithmetic for DSP Systems , 1994 .

[16]  T. Bially,et al.  Parallelism in fast Fourier transform hardware , 1973 .