Track assignment: a desirable intermediate step between global routing and detailed routing
暂无分享,去创建一个
[1] C.-J. Richard Shi. Solving constrained via minimization by compact linear programming , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.
[2] Chak-Kuen Wong,et al. Layer assignment for multichip modules , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] David S. Johnson,et al. Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .
[4] Joseph Y.-T. Leung,et al. An Optimal Solution for the Channel-Assignment Problem , 1979, IEEE Transactions on Computers.
[5] Jason Cong,et al. DUNE: a multi-layer gridless routing system with wire planning , 2000, ISPD '00.
[6] Asmus Hetzel,et al. A sequential detailed router for huge grid graphs , 1998, Proceedings Design, Automation and Test in Europe.
[7] Carl Sechen,et al. Timing- and crosstalk-driven area routing , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Takeshi Yoshimura,et al. Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Sung-Mo Kang,et al. Detailed layer assignment for MCM routing , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[10] Gary L. Miller,et al. The Complexity of Coloring Circular Arcs and Chords , 1980, SIAM J. Algebraic Discret. Methods.
[11] Frank Harary,et al. Graph Theory , 2016 .
[12] Majid Sarrafzadeh,et al. Restricted track assignment with applications , 1994, Int. J. Comput. Geom. Appl..
[13] Sung-Mo Kang,et al. Crosstalk-minimum layer assignment , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
[14] Naveed A. Sherwani,et al. Algorithms for VLSI Physical Design Automation , 1999, Springer US.
[15] Jason Cong,et al. An efficient approach to multilayer layer assignment with anapplication to via minimization , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[16] C. L. Liu,et al. Optimization of the maximum delay of global interconnects duringlayer assignment , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[17] Naveed A. Sherwani. Algorithms for VLSI Physcial Design Automation , 1998 .
[18] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[19] T. C. Chern,et al. Fast algorithm for optimal layer assignment , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[20] Maciej J. Ciesielski,et al. Layer assignment for VLSI interconnect delay minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[21] Jason Cong,et al. Pseudo pin assignment with crosstalk noise control , 2000, ISPD '00.