Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks

Energy-efficient and reliable channels are provided for on-chip interconnection networks (OCINs) using a self-calibrated voltage scaling technique with self-corrected green (SCG) coding scheme. This self-calibrated low-power coding and voltage scaling technique increases reliability and reduces energy consumption simultaneously. The SCG coding is a joint bus and error correction coding scheme that provides a reliable mechanism for channels. In addition, it achieves a significant reduction in energy consumption via a joint triplication bus power model for crosstalk avoidance. Based on SCG coding scheme, the proposed self-calibrated voltage scaling technique adjusts voltage swing for energy reduction. Furthermore, this technique tolerates timing variations. Based on UMC 65 nm CMOS technology, the proposed channels reduces energy consumption by nearly 28.3% compared with that for uncoded channels at the lowest voltage. This approach makes the channels of OCINs tolerant of transient malfunctions and realizes energy efficiency.

[1]  Rung-Bin Lin,et al.  Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Sung-Mo Kang,et al.  A low energy encoding technique for reduction of coupling effects in SoC interconnects , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[3]  Giovanni De Micheli,et al.  A robust self-calibrating transmission scheme for on-chip networks , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[5]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[6]  Abhijit Chatterjee,et al.  Switching activity generation with automated BIST synthesis forperformance testing of interconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Massoud Pedram,et al.  Architectures for silicon nanoelectronics and beyond , 2007, Computer.

[8]  Bo Fu,et al.  On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Sung-Mo Kang,et al.  Coupling-driven signal encoding scheme for low-power interface design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[10]  Davide Bertozzi,et al.  Variation tolerant NoC design by means of self-calibrating links , 2008, 2008 Design, Automation and Test in Europe.

[11]  Naresh R. Shanbhag,et al.  Coding for reliable on-chip buses: fundamental limits and practical codes , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[12]  R. Ho.  Chip Wires: Scaling and Efficiency , 2003 .

[13]  Igor L. Markov,et al.  Error-correction and crosstalk avoidance in DSM busses , 2004, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Paul-Peter Sotiriadis,et al.  Interconnect modeling and optimization in deep sub-micron technologies , 2002 .

[15]  Mani B. Srivastava,et al.  A survey of techniques for energy efficient on-chip communication , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[16]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Luca Benini,et al.  Timing-Error-Tolerant Network-on-Chip Design Methodology , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Jörg Henkel,et al.  ETAM++: extended transition activity measure for low power address bus designs , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[19]  Saeid Nooshabadi,et al.  Analysis and design of memoryless interconnect encoding scheme , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[20]  M.A. Elgamel,et al.  Interconnect noise analysis and optimization in deep submicron technology , 2003, IEEE Circuits and Systems Magazine.

[21]  Partha Pratim Pande,et al.  Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.

[22]  Jörg Henkel,et al.  An adaptive dictionary encoding scheme for SOC data buses , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[23]  Naresh R. Shanbhag,et al.  Coding for reliable on-chip buses: a class of fundamental bounds and practical codes , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  M. Horowitz,et al.  Efficient on-chip global interconnects , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[25]  Sujit Dey,et al.  Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Hoi-Jun Yoo,et al.  Low-power network-on-chip for high-performance SoC design , 2006, IEEE Trans. Very Large Scale Integr. Syst..

[27]  Luca Benini,et al.  On-Chip Communication Architectures: System on Chip Interconnect , 2008 .

[28]  Chun-Gi Lyuh,et al.  Low power bus encoding with crosstalk delay elimination [SoC] , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[29]  Sujit Dey,et al.  LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects , 2003, J. Electron. Test..

[30]  Alexandre Yakovlev,et al.  Phase-Encoding for On-Chip Signalling , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[31]  Partha Pratim Pande,et al.  Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[32]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[33]  Sujit Dey,et al.  Self-test methodology for at-speed test of crosstalk in chip interconnects , 2000, DAC.

[34]  Anantha Chandrakasan,et al.  A bus energy model for deep submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[35]  Giovanni De Micheli,et al.  Self-calibrating networks-on-chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[36]  Sanu Mathew,et al.  A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[37]  Jun Yang,et al.  FV encoding for low-power data I/O , 2001, ISLPED '01.

[38]  Naresh R. Shanbhag,et al.  Coding for system-on-chip networks: a unified framework , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[39]  N. Shlayan,et al.  Review of Packet Switching Technologies for Future NoC , 2008, 2008 19th International Conference on Systems Engineering.

[40]  Zhiyi Yu,et al.  A 167-Processor Computational Platform in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[41]  Taewhan Kim.  Low Power Bus Encoding with Crosstalk Delay Elimination , 2002 .

[42]  Partha Pratim Pande,et al.  Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.