A 10-bit 400 MS/s asynchronous SAR ADC using dual-DAC architecture for speed enhancement
暂无分享,去创建一个
[1] Rui Paulo Martins,et al. An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS , 2016, IEEE Journal of Solid-State Circuits.
[2] Chun-Cheng Liu,et al. A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS , 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).
[3] Po-Chiun Huang,et al. A 0.003 mm$^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching , 2015, IEEE Journal of Solid-State Circuits.
[4] Nan Sun,et al. A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOS , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.
[5] Patrick Chiang,et al. Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS , 2010, IEEE Custom Integrated Circuits Conference 2010.
[6] Ho-Jin Park,et al. An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.