A universal testability strategy for multi-chip modules based on BIST and boundary-scan

A testability strategy that can be implemented mainly by incorporating built-in self-test (BIST) and boundary scan during the chip design cycle is presented. On the basis of these, the testing and diagnosis procedures needed to meet the quality requirements of multichip module (MCM) manufacturing, and hence reaching acceptable MCM assembly yields is demonstrated. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate, or attachment technologies adopted to build the MCM.<<ETX>>

[1]  M. M. Pradhan,et al.  Circular BIST with partial scan , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[2]  Y. Zorian A structured approach to macrocell testing using built-in self-test , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[3]  Kenneth E. Posse A DESIGN-FOR-TESTABILITY ARCHITECTURE FOR MULTICHIP MODULES , 1991, 1991, Proceedings. International Test Conference.

[4]  Parker,et al.  Design for Testability—A Survey , 1982, IEEE Transactions on Computers.

[5]  Najmi T. Jarwala,et al.  The boundary-scan master: target applications and functional requirements , 1990, Proceedings. International Test Conference 1990.

[6]  A.J. van de Goor,et al.  Functional tests for arbitration SRAM-type FIFOs , 1992, Proceedings First Asian Test Symposium (ATS `92).

[7]  W. David Ballew,et al.  Board-level boundary-scan: regaining observability with an additional IC , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[8]  Yervant Zorian,et al.  An Effective BIST Scheme for ROM's , 1992, IEEE Trans. Computers.

[9]  Partha Raghavachari,et al.  CIRCUIT PACK BIST FROM SYSTEM TO FACTORY - THE MCERT CHIP , 1991, 1991, Proceedings. International Test Conference.

[10]  D. C. Keezer Bare die testing and MCM probing techniques , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[11]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .

[12]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[13]  J. Kessler,et al.  Multichip module testing , 1988 .

[14]  R.R. Johnson Multichip modules: next-generation packages , 1990, IEEE Spectrum.

[15]  J. K. Hagge,et al.  State-of-the-art multichip modules for avionics , 1991 .

[16]  Thomas W. Williams,et al.  Design for Testability - A Survey , 1982, IEEE Trans. Computers.

[17]  R. H. Parker Bare die test , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[18]  Robert J. Wojnarowski,et al.  Bare chip test techniques for multichip modules , 1990, 40th Conference Proceedings on Electronic Components and Technology.

[19]  Najmi T. Jarwala,et al.  A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[20]  F. Hohn,et al.  Background and applications of electron beam test techniques , 1986 .