A 1MHz-bandwidth type-I ΔΣ fractional-N synthesizer for WiMAX applications

A major source of close-in phase noise in ΔΣ fractional-N frequency synthesizers is noise-folding due to the nonlinear behavior of the combined phase-frequency detector (PFD)/charge-pump (CP) circuit. A fractional-N PLL with an analog discrete-time PFD and loop filter, along with an error cancelling DAC is utilized to alleviate the impact of ΔΣ quantization error and nonlinearities on the phase noise and spurious emissions. In comparison to Type-II PLL, this design suffers less quantization noise folding because the ΔΣ quantization noise goes through phase error transfer function with better linearity. A two-state Type-I loop replaces the more conventional Type-II charge-pump PLLs where a tri-state PFD/CP produces a current proportional to phase error [1]. The Type-I loop shifts the operating point of the phase detector away from the nonlinear region (i.e., close to zero phase error), thus eliminating the need for special CP linearization techniques [2–4]. The architecture of the PLL is depicted in Fig. 23.1.1. In this architecture, a third-order re-quantization path along with an 8b current-steering DAC reduces quantization noise induced phase error by more than 20dB, enabling a wide loop bandwidth of 1MHz.