A single-motion-vector/cycle-generation optical flow processor employing directional-edge histogram matching

A VLSI optical flow processor capable of generating a single motion vector at every clock cycle has been developed. By employing a directional-edge histogram matching, the computational cost has been reduced and the influence of illumination change has been alleviated as well. In order to generate an edge histogram in a single clock cycle, a special data allocation scheme in on-chip SRAM banks has been developed. In addition, a parallel shift and matching architecture using compact absolute difference circuits has been introduced. As a result, single-motion-vector/cycle generation from an arbitrary pixel location has been established. A prototype chip was fabricated in a 0.18-µm 5-metal CMOS technology and the measurement results demonstrated about 1,000 times faster performance at a clock frequency of 20MHz than the software processing using a 2.8-GHz CPU.

[1]  T. Shibata,et al.  A real-time image-feature-extraction and vector-generation VLSI employing arrayed-shift-register architecture , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[2]  Tadashi Shibata,et al.  Illumination-invariant face identification using edge-based feature vectors in pseudo-2D Hidden Markov Models , 2006, 2006 14th European Signal Processing Conference.

[3]  Tadashi Shibata,et al.  A Vlsi-Implementation-Friendly EGO-Motion Detection Algorithm Based on Edge-Histogram Matching , 2006, 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings.

[4]  Anil K. Jain,et al.  Displacement Measurement and Its Application in Interframe Image Coding , 1981, IEEE Trans. Commun..

[5]  Gealow,et al.  A Pixel-parallel Image Processor Using Logic Pitch-matched To Dynamic Memory , 1997, Symposium 1997 on VLSI Circuits.

[6]  Tadashi Shibata,et al.  An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems , 2003, IEEE Trans. Neural Networks.

[7]  Tzi-Dar Chiueh,et al.  An analog motion field detection chip for image segmentation , 2002, IEEE Trans. Circuits Syst. Video Technol..

[8]  Berthold K. P. Horn,et al.  Determining Optical Flow , 1981, Other Conferences.

[9]  Ralph Etienne-Cummings,et al.  Normal Optical Flow measurement on a CMOS APS imager , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[10]  M. Ishikawa,et al.  A dynamically reconfigurable SIMD processor for a vision chip , 2003, IEEE Journal of Solid-State Circuits.

[11]  Ralph Etienne-Cummings,et al.  Normal optical flow measurement on CMOS APS imager , 2005 .

[12]  T. Shibata,et al.  A Feature-Based Optical Flow Processor Architecture Featuring Single-Motion-Vector/Cycle Generation , 2007, 2007 International Symposium on System-on-Chip.

[13]  Alan A. Stocker,et al.  Computation of Smooth Optical Flow in a Feedback Connected Analog Network , 1998, NIPS.