Performance Enhancement by Optimization of Poly Grain Size and Channel Thickness in a Vertical Channel 3-D NAND Flash Memory

String read current (<inline-formula> <tex-math notation="LaTeX">${I}_{\textsf {read}}$ </tex-math></inline-formula>) reduction with rising mold height and grain boundary traps is one of the major hurdle in the development of 3-D NAND flash memory. In this paper, we have investigated <inline-formula> <tex-math notation="LaTeX">${I}_{\textsf {read}}$ </tex-math></inline-formula> with variation in polysilicon channel grain size (GS), grain boundary trap density, and channel thickness (<inline-formula> <tex-math notation="LaTeX">${T}_{\textsf {Si}}$ </tex-math></inline-formula>), using TCAD. We find that under a critical value of GS, <inline-formula> <tex-math notation="LaTeX">${I}_{\textsf {read}}$ </tex-math></inline-formula> decreases with increase in <inline-formula> <tex-math notation="LaTeX">${T}_{\textsf {Si}}$ </tex-math></inline-formula>. This is attributed to the fact that with smaller GS, the total number of grain boundaries and associated traps are significantly higher. Moreover, there exists a typical value of GS for which <inline-formula> <tex-math notation="LaTeX">${I}_{\textsf {read}}$ </tex-math></inline-formula> is independent of <inline-formula> <tex-math notation="LaTeX">${T}_{\textsf {Si}}$ </tex-math></inline-formula>, which is desirable to minimize the deviations in <inline-formula> <tex-math notation="LaTeX">${I}_{\textsf {read}}$ </tex-math></inline-formula> arising from <inline-formula> <tex-math notation="LaTeX">${T}_{\textsf {Si}}$ </tex-math></inline-formula> variations. The resulting tradeoff in the design of more efficient 3-D NAND flash is demonstrated and discussed. Further, it is found that <inline-formula> <tex-math notation="LaTeX">${I}_{\textsf {read}}$ </tex-math></inline-formula> increases significantly by limiting the polysilicon channel grain boundary trap concentration under 10¹² cm⁻². The results presented in this paper are crucial for optimizing <inline-formula> <tex-math notation="LaTeX">${I}_{\textsf {read}}$ </tex-math></inline-formula> and program/erase threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula>) window, and serve as key guidelines in the design of 3-D NAND flash memory with better performance.