Towards Generic Embedded Multiprocessing for RVC-CAL Dataflow Programs

Dataflow languages enable describing signal processing applications in a platform independent fashion, which makes them attractive in today’s multiprocessing era. RVC-CAL is a dynamic dataflow language that enables describing complex data-dependent programs such as video decoders. To this date, design automation toolchains for RVC-CAL have enabled creating workstation software, dedicated hardware and embedded application specific multiprocessor implementations out of RVC-CAL programs. However, no solution has been presented for executing RVC-CAL applications on generic embedded multiprocessing platforms. This paper presents a dataflow-based multiprocessor communication model, an architecture prototype that uses it and an automated toolchain for instantiating such a platform and the software for it. The complexity of the platform increases linearly as the number of processors is increased. The experiments in this paper use several instances of the proposed platform, with different numbers of processors. An MPEG-4 video decoder is mapped to the platform and executed on it. Benchmarks are performed on an FPGA board.

[1]  Ghislain Roquier,et al.  Synthesizing Hardware from Dataflow Programs , 2008, 2008 IEEE Workshop on Signal Processing Systems.

[2]  Mickaël Raulet,et al.  Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs , 2011, 2011 IEEE Workshop on Signal Processing Systems (SiPS).

[3]  Henk Corporaal.  Microprocessor architectures - from VLIW to TTA , 1997 .

[4]  Mickaël Raulet,et al.  Reconfigurable video coding: a stream programming approach to the specification of new video coding standards , 2010, MMSys '10.

[5]  E.A. Lee,et al.  Synchronous data flow , 1987, Proceedings of the IEEE.

[6]  Mickaël Raulet,et al.  Automatic Hierarchical Discovery of Quasi-Static Schedules of RVC-CAL Dataflow Programs , 2013, J. Signal Process. Syst..

[7]  Hemangee K. Kapoor,et al.  Exploring Use of NoC for Reconfigurable Video Coding , 2010, 2010 23rd International Conference on VLSI Design.

[8]  Jack B. Dennis,et al.  A preliminary architecture for a basic data-flow processor , 1974, ISCA '98.

[9]  Mickaël Raulet,et al.  Efficient multicore scheduling of dataflow process networks , 2011, 2011 IEEE Workshop on Signal Processing Systems (SiPS).

[10]  Ghislain Roquier,et al.  Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study , 2008, SiPS.

[11]  Jarmo Takala,et al.  Customized Exposed Datapath Soft-Core Design Flow with Compiler Support , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[12]  Jani Boutellier,et al.  Application-specific instruction processor for extracting local binary patterns , 2012, Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing.