Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
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[1] Jay M. Berger. A Note on Error Detection Codes for Asymmetric Channels , 1961, Inf. Control..
[2] Bella Bose,et al. Systematic Unidirectional Error-Detecting Codes , 1985, IEEE Transactions on Computers.
[3] Jacob A. Abraham,et al. DESIGN OF PLAS WITH CONCURRENT ERROR DETECTION. , 1982 .
[4] D. A. Anderson,et al. Design of self-checking digital networks using coding techniques , 1971 .
[5] Michael Nicolaidis,et al. Self-exercising checkers for unified built-in self-test (UBIST) , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Prithviraj Banerjee,et al. RSYN: a system for automated synthesis of reliable multilevel circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[7] Michael Nicolaidis,et al. New implementations, tools, and experiments for decreasing self-checking PLAs area overhead , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[8] Alberto L. Sangiovanni-Vincentelli,et al. MUSTANG: state assignment of finite state machines targeting multilevel logic implementations , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Niraj K. Jha,et al. Design and synthesis of self-checking VLSI circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] S.K. Gupta,et al. Can concurrent checkers help BIST? , 1992, Proceedings International Test Conference 1992.
[11] Vl. V. Saposhnikov,et al. A New Design Method for Self-Checking Unidirectional Combinational Circuits , 1998, J. Electron. Test..
[12] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] K. Keutzer. DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, 24th ACM/IEEE Design Automation Conference.
[14] Niraj K. Jha. Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[15] Bella Bose,et al. A self-checking ALU design with efficient codes , 1996, Proceedings of 14th VLSI Test Symposium.
[16] Suchai Thanawastien,et al. An SFS Berger check prediction ALU and its application to self-checking processor designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[17] Dhiraj K. Pradhan,et al. Fault-tolerant computing : theory and techniques , 1986 .
[18] James E. Smith,et al. Strongly Fault Secure Logic Networks , 1978, IEEE Transactions on Computers.
[19] Steffen Graf,et al. Error Detection Circuits , 1993 .