A low power 8-tap digital FIR filter for PRML read channels
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Soo-Won Kim | Kwanyeob Chae | In-Chul Hwang | Hoon Jae Ki | Woo Hyun Paik | Cheon Su Lee | Jang Sik Yoo
[1] L. E. Thon,et al. A 240 MHz 8-trap programmable FIR filter for disk-drive read channels , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.
[2] W. L. Abbott,et al. A digital chip with adaptive equalizer for PRML detection in hard-disk drives , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
[3] Scott K. Reynolds,et al. Digital FIR filters for high speed PRML disk read channels , 1995 .
[4] Marco Annaratone. Digital CMOS Circuit Design , 1986 .
[5] Hoon Jae Ki,et al. Low power logic design using push-pull pass-transistor logics , 1998 .
[6] Soo-Won Kim,et al. A high speed, low power 8-tap digital FIR filter for PRML disk-drive read channels , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.
[7] G. D. Fisher,et al. PRML detection boosts hard-disk drive capacity , 1996 .
[8] Jacques C. Rudell,et al. A 50 MHz eight-tap adaptive equalizer for partial-response channels , 1995 .
[9] Rinaldo Castello,et al. A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo , 1997 .
[10] David Moloney,et al. Low-power 200-Msps, area-efficient, five-tap programmable FIR filter [in BiCMOS] , 1998 .
[11] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[12] G. Feygin,et al. A 160 MHz analog equalizer for magnetic disk read channels , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[13] Makoto Suzuki,et al. A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer , 1995 .