Reliability in the Shadow of Long-Stall Instructions

Soft errors due to cosmic rays are now a major concern for both computer manufacturers and end users. Due to continually shrinking silicon manufacturing processes and greater chip integration, the chipand system-level soft error rate is projected to continue increasing for the forseeable future. Du e to these concerns, chip manufacturers have long designed cache structures (generally the largest on-chip structures in a highperformance processor) to include protection techniques such a s parity or ECC. In order to meet SER targets, new chip designs are starting to incorporate such protection on physical register files. As the soft error rate increases, however, large processo r pipeline structures will also require protection against soft errors. Unfortunately, many of these pipeline structures are latencycritical, needing to complete multiple accesses per processor cycle. Thus, many of these structures are ill-suited for protectio n techniques such as ECC, which can add latency to each access. In modern processors, these structures typically contain inflight instructions, which can vary in their vulnerability contribution. Thus, uniform protection such as that provided by ECC may not be necessary. Our goal is to explore and explain some of the underlying causes of this variation in vulnerability among instructions. In this study, we examine the vulnerability contribution of instructions that are in-flight during (in the shadow of) long-stall instructions, which will define the maximum potential benefit of techniques that exploit these stall cycles.