Phase change memory device having characteristic of peak current decrease and data writing method therefor

The phase change memory device having the phase change memory cell and the data writing method is initiated accordingly. The phase change memory device according to the present invention is coupled to a plurality of bit lines and a plurality of word lines and a plurality of phase change memory cell, the bit line connected to each intersection of the plurality of bit lines and a plurality of word lines to each other a reset pulse having a different active period and a plurality of write drivers respectively supplied to the bit lines in which the corresponding. According to the phase change memory device according to the present invention, the peak current value is decreased or minimized in the write operation is a variation in the power supply voltage is significantly prevented. Therefore, there is an advantage that the write operation performance of a phase change memory device improved so reduces the fail probability of a write operation at the same time increasing the number of light available bits. The phase change memory, the write data, three current pulses, a reset current pulse