Multiprocessor implementation of 2-D denominator-separable digital filters for real-time processing

The problem of realizing 2-D denominator-separable digital filters is considered. Four realizations are derived with emphasis on real-time processing in a multiprocessor environment. This implies maximizing parallelism and pipelining, minimizing data throughput delay, and developing computational primitives which can be used as building blocks for very-large-scale integrated-circuit (VLSI) implementation. Advantage is taken of well-known realization structures for 1-D systems in developing the derivations. The performance of each realization is evaluated using criteria appropriate for real-time processing and multiprocessor implementation. It is shown that a simple computational primitive of one multiplier and one adder can be used to realize the filter with data throughput delay time equal to the time required for one multiplication and one addition, independent of the order of the filter. However, the number of required processors is different for each realization, and thus each realization has a different efficiency measure. >

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