A System Level Boundary Scan Controller Board for VME Applications

In this article an application of boundary scan test at system level is analyzed. The objective is met through the description of the design and implementation options of a VME boundary scan controller board prototype and the corresponding software. The prototype board uses the MTM bus, existing in the VME64x backplane, to apply the IEEE 1149.1 test vectors to one of the sixty four sub-systems, each one composed by nineteen boards. The software being developed uses the boundary scan test vectors generated by an ATPG in SVF format, and converts them into a format suitable to be used in our test system. Test results consists in a pass/fail assessment. Further diagnosis information about fault location requires the utilization of an additional software test tool. After giving some insights about the experiment where this hardware is required, the paper describes the boundary scan test architecture at system and board level, the test development tools used in the experience environment, the test of the boundary scan controller board prototype and the software used to interface the board with the ATPG. The results obtained so far and the proposed work is reviewed in the end of this contribution. This work is the result of a collaboration between INESC and LIP in the Compact Muon Solenoid experiment being conducted at CERN.