Low-power state-retention dual edge-triggered pulsed latch

This paper presents a new state retention pulsed latch suitable for low-power and high speed applications. The proposed circuit employs power-gating during idle mode to reduce leakage power, while retaining its state. The pulsed structure of the circuit makes it feasible to be used in high speed designs. The HSPICE simulation conducted for 45nm CMOS technology indicates that in addition to state retention the proposed design, in terms of power-delay product (PDP), device count, and leakage power is comparable to other high performance flip-flops.

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