Cognitive Artificial Intelligence Countermeasure for Enhancing the Security of Big Data Hardware from Power Analysis Attack

Digital communication systems as the part of big data are utilized to transmit data and information. The increase of the digital communication system utilization will increase the value of information and on the other hand also induces an increase in the number of attacks on such systems. Side Channel Attack (SCA) is an attack model that could disrupt the information security when hardware implements a cryptographic algorithm. Differential Power Analysis (DPA), a kind of SCA, can reveal 75% of secret key used in encryption hardware. Other techniques called Correlation Power Analysis (CPA) which uses correlation factor between trace and hamming weight from the input of key generation can reveal the right secret key of Advanced Encryption Standard (AES) in significantly shorter span of time. The objective of this research is to design and implement an electronic countermeasure to deal with power analysis attack. The attacking aspect is reviewed as a form of identification of the correct countermeasure method against power analysis attack using Cognitive Artificial Intelligence (CAI)‘s method called cognitive countermeasure approach in an AES encryption device. Our main contribution is in the design of cognitive-countermeasure by altering the measured power consumption in affecting the secret key value of power analysis. The measured signal is altered by generating random masking value using CAI’s information fusion. CAI is a new perspective in Artificial Intelligence which is characterized by its capability to grow new knowledge based on the information from the sensory system. The random alteration of measured signal and continuous evolution of the masking value by using CAI’s information fusion is very significant in tackling the risk of power analysis. We also succeeded in implementing an AES encryption device based on CAI method on the Field-Programmable Gate Array (FPGA) platform.

[1]  Francis Chung-Ming Lau,et al.  A high throughput Gaussian noise generator , 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

[2]  Paul Dischamp,et al.  Power Analysis, What Is Now Possible , 2000, ASIACRYPT.

[3]  Aciek Ida Wuryandari,et al.  Constructing brain-inspired knowledge-growing system: A review and a design concept , 2010, 2010 International Conference on Distributed Frameworks for Multimedia Applications.

[4]  Adang Suwandi Ahmad,et al.  Design of an AES Device as Device Under Test in a DPA Attack , 2018, Int. J. Netw. Secur..

[5]  Adang Suwandi Ahmad,et al.  Design and Implementation of Multi Agent­based Information Fusion System for Decision Making Support (A Case Study on Military Operation) , 2008 .

[6]  Vincent Rijmen,et al.  The Design of Rijndael , 2002, Information Security and Cryptography.

[7]  Paul C. Kocher,et al.  Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.

[8]  Jovan Dj. Golic,et al.  Multiplicative Masking and Power Analysis of AES , 2002, CHES.

[9]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[10]  Antoine Joux,et al.  Algorithmic Cryptanalysis , 2009 .

[11]  Umar Khayam,et al.  Cognitive artificial-intelligence for doernenburg dissolved gas analysis interpretation , 2019 .

[12]  Adang Suwandi Ahmad,et al.  Attacking AES-Masking Encryption Device with Correlation Power Analysis , 2018, Int. J. Commun. Networks Inf. Secur..

[13]  Thomas S. Messerges,et al.  Investigations of Power Analysis Attacks on Smartcards , 1999, Smartcard.

[14]  Aciek Ida Wuryandari,et al.  Brain-Inspired Knowledge-Growing System: Towards a True Cognitive Agent , 2012 .

[15]  Subrata Das.  High-Level Data Fusion , 2008 .

[16]  Henk L. Muller,et al.  Random Register Renaming to Foil DPA , 2001, CHES.

[17]  Pankaj Rohatgi,et al.  Introduction to differential power analysis , 2011, Journal of Cryptographic Engineering.

[18]  Jie Li,et al.  A side-channel analysis resistant reconfigurable cryptographic coprocessor supporting multiple block cipher algorithms , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[19]  Christophe Giraud,et al.  An Implementation of DES and AES, Secure against Some Attacks , 2001, CHES.

[20]  Christophe Clavier,et al.  Correlation Power Analysis with a Leakage Model , 2004, CHES.

[21]  Arwin Datumaya Wahyudi Sumari,et al.  Revealing AES Encryption Device Key on 328P Microcontrollers with Differential Power Analysis , 2018 .

[22]  Lilian Bossuet,et al.  Correlated power noise generator as a low cost DPA countermeasures to secure hardware AES cipher , 2009, 2009 3rd International Conference on Signals, Circuits and Systems (SCS).

[23]  Lilian Bossuet,et al.  A masked Correlated Power Noise Generator use as a second order DPA countermeasure to secure hardware AES cipher , 2011, ICM 2011 Proceeding.