Impact of Gate Induced Drain Leakage and Impact Ionization Currents on Hysteresis Modeling of PD SOI Circuits

The impact of the gate induced drain leakage and impact ionization currents on hysteresis of PD FB SOI circuits is examined, and a physical understanding is provided. Measured silicon data from 90nm and 65nm PD SOI technologies indicate that both components dominate in the substrate currents at zero gate voltage and non-zero drain voltages. Substrate currents under these particular conditions are critical to pre-first-switch body voltage establishment, which is definitively validated by a compact modeling experiment. As the OFF-state channel leakage current increases in scaled technologies, these substrate currents need to be closely monitored and well modeled to properly predict and understand evolution of the hysteresis behavior.

[1]  Qiang Chen,et al.  An A Priori Hysteresis Modeling Methodology for Improved Efficiency and Model Accuracy in Advanced PD SOI Technologies , 2005 .

[2]  M. Sherony,et al.  Impact of the gate-to-body tunneling current on SOI history effect , 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

[3]  Norman J. Rohrer,et al.  SOI circuit design concepts , 2000 .

[4]  T.Y. Chan,et al.  The impact of gate-induced drain leakage current on MOSFET scaling , 1987, 1987 International Electron Devices Meeting.

[5]  Edward J. Nowak,et al.  Predicting the SOI History Effect Using Compact Models , 2004 .

[6]  Zhi-Yuan Wu,et al.  History-effect-conscious SPICE model extraction for PD-SOI technology , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).