An Ultra Low-power Low-offset Double-tail Comparator

In double tail comparators, the pre-amplifier amplifies the input differential voltage and when the output Vcm of the pre-amplifier becomes larger than Vth of the latch input transistors, the latch is activated and finalizes the comparison. As a result, the pre-amplification delay is fixed to a value and cannot be set at the minimum required delay, to save power and improve offset. In fact, when the latch is activated the pre-amplifier output differential voltage is still growing but the latch finishes the comparison before the maximum differential gain is formed and applied to the latch. In this paper, a comparator is proposed in which the preamplifier is turned off when the maximum gain is achieved so that always the maximum possible gain is applied to the latch. Therefore, not only the input referred offset is improved but also the power consumption of the pre-amplifier is saved. Simulations in 0.18µm technology show with an appropriate pre-amplification delay the average power is saved by up to 75% while the offset voltage is reduced by about 30%.

[1]  Qiang Li,et al.  High-speed low-power common-mode insensitive dynamic comparator , 2015 .

[2]  Pedro M. Figueiredo,et al.  Kickback noise reduction techniques for CMOS latched comparators , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Eric A. M. Klumperink,et al.  A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[4]  Andrea Baschirotto,et al.  A 7.65-mW 5-bit 90-nm 1-Gs/s Folded Interpolated ADC Without Calibration , 2014, IEEE Transactions on Instrumentation and Measurement.

[5]  Jeremy Holleman,et al.  A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Mohammad Sharifkhani,et al.  A low-power low-offset dynamic comparator for analog to digital converters , 2014, Microelectron. J..

[7]  D. Jeong,et al.  Ultra‐low‐voltage low‐power dynamic comparator with forward body bias scheme for SAR ADC , 2018, Electronics Letters.

[8]  Gabor C. Temes,et al.  Low-power and low-offset comparator using latch load , 2011 .

[9]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[10]  Ata Khorami,et al.  A Low-Power High-Speed Comparator for Precise Applications , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Kunihiro Asada,et al.  Clocked comparator for high-speed applications in 65nm technology , 2010, 2010 IEEE Asian Solid-State Circuits Conference.

[12]  Ata Khorami,et al.  An ultra low-power DAC with fixed output common mode voltage , 2018 .

[13]  Ata Khorami,et al.  A low-power technique for high-resolution dynamic comparators , 2018, Int. J. Circuit Theory Appl..

[14]  Ata Khorami,et al.  Elimination of the effect of bottom-plate capacitors in C-2C DAC using a layout technique , 2015, Microelectron. J..

[15]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .

[16]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[17]  Ata Khorami,et al.  High-speed low-power comparator for analog to digital converters , 2016 .

[18]  Ata Khorami,et al.  Low-power technique for dynamic comparators , 2016 .

[19]  Xin Xin,et al.  Ultra-low power comparator with dynamic offset cancellation for SAR ADC , 2017 .

[20]  Reza Lotfi,et al.  Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Ata Khorami,et al.  A low-power high-speed comparator for analog to digital converters , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).