Underfill Flow Void Solutions Through Process and Materials Interaction

Silicon dies were thinned down and bump pitch became smaller to have a lot of input/output in electronic device packages especially in package on package configuration. This presents challenges on underfill (UF) dispense processing. UF voids occurred near the dispense side of bumps in multiple dispense pass technology. In this paper, we will review UF flow behavior on thin die technology, as well as the process and material interaction that cause UF void formation. Process optimization, such as the time between two dispense passes has become a critical parameter to eliminate UF voids without causing UF epoxy roll up that can cause reliability failure.

[1]  K. H. Chua,et al.  Study on Factors Affecting Underfill Flow and Underfill Voids in a Large-die Flip Chip Ball Grid Array (FCBGA) Package , 2007, 2007 9th Electronics Packaging Technology Conference.

[2]  Jinlin Wang The effect of flux residue and substrate wettability on underfill flow process in flip chip packages , 2006, 56th Electronic Components and Technology Conference 2006.

[3]  A. Babiarz,et al.  Best practices in automated underfill dispensing , 1998, Proceedings of 2nd Electronics Packaging Technology Conference (Cat. No.98EX235).

[4]  J. Yoo,et al.  Computational Fluid Dynamics 2008 , 2009 .