Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p<sup>+</sup>-i- n<sup>+</sup> tunneling junction, the TFET with a gate length of ~ 200 nm exhibits good subthreshold swing of ~ 70 mV/dec, superior drain-induced-barrier-lowering of ~ 17 mV/V, and excellent <i>I</i> <sub>on</sub> - <i>I</i> <sub>off</sub> ratio of ~ 10<sup>7</sup> with a low <i>I</i> <sub>off</sub> ( ~ 7&nbsp;pA/mum). The obtained 53 muA/mum <i>I</i> <sub>on</sub> can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.

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