A timing-driven pseudoexhaustive testing for VLSI circuits
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[1] Edward J. McCluskey. Verification Testing - A Pseudoexhaustive Test Technique , 1984, IEEE Trans. Computers.
[2] D. R. Fulkerson,et al. Flows in Networks. , 1964 .
[3] Melvin A. Breuer,et al. An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing , 1993, 30th ACM/IEEE Design Automation Conference.
[4] Wen-Ben Jone,et al. A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] M. W. Roberts,et al. An algorithm for the partitioning of logic circuits , 1984 .
[6] Edward J. McCluskey,et al. Design for Autonomous Test , 1981, IEEE Transactions on Computers.
[7] Giovanni De Micheli,et al. Synthesis and Optimization of Digital Circuits , 1994 .
[8] Jason Cong,et al. FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Jacob Savir,et al. Built In Test for VLSI: Pseudorandom Techniques , 1987 .
[10] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[11] George Markowsky,et al. The Weighted Syndrome Sums Approach to VLSI Testing , 1981, IEEE Transactions on Computers.
[12] Kurt Keutzer,et al. Logic Synthesis , 1994 .
[13] Narsingh Deo,et al. Graph Theory with Applications to Engineering and Computer Science , 1975, Networks.
[14] Kwang-Ting Cheng,et al. Timing-driven test point insertion for full-scan and partial-scan BIST , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).