Modeling and simulation of circuits with shared structurally synthesized BDDs

Abstract Modeling and simulation are critical tools for the analysis of testability and verification of digital circuits. BDDs are a well-known model for manipulating Boolean functions. However, the traditional BDDs mainly address modeling the function of the digital circuits, and not the structural aspects that are important for testability analysis. We propose a new type of BDD in the form of Shared Structurally Synthesized BDD (S 3 BDD) for representing the structure and simulating the faults in digital circuits. The paper presents a method for synthesis of S 3 BDDs, offers a formula for calculating the minimal size of the model, and proposes a method for parallel pattern simulation with S 3 BDDs We demonstrate a considerable increase in the speed-up of simulation of digital circuits using S 3 BDDs.

[1]  Raimund Ubar,et al.  Structurally synthesized multiple input BDDs for simulation of digital circuits , 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

[2]  Giovanni Squillero,et al.  RT-Level ITC'99 Benchmarks and First ATPG Results , 2000, IEEE Des. Test Comput..

[3]  Raimund Ubar,et al.  Fault simulation with parallel exact critical path tracing in multiple core environment , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Jaakko Astola,et al.  Spectral Logic and Its Applications for the Design of Digital Devices , 2008 .

[5]  Raimund Ubar,et al.  Test Synthesis with Alternative Graphs , 1996, IEEE Des. Test Comput..

[6]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[7]  Raimund Ubar,et al.  Multiple stuck-at-fault detection theorem , 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

[8]  Rolf Drechsler,et al.  Minimization of free BDDs , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[9]  Raimund Ubar,et al.  Parallel X-fault simulation with critical path tracing technique , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[10]  Chen-Shang Lin,et al.  On the OBDD-Representation of General Boolean Functions , 1992, IEEE Trans. Computers.

[11]  Raimund Ubar,et al.  Combinational fault simulation in sequential circuits , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[12]  A. Lloy,et al.  Advanced fault collapsing (logic circuits testing) , 1992 .

[13]  Raimund Ubar,et al.  Lower bounds of the size of Shared Structurally Synthesized BDDs , 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

[14]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[15]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[16]  Heinrich Theodor Vierhaus,et al.  Design and Test Technology for Dependable Systems-on-Chip , 2010 .

[17]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[18]  Raimund Ubar,et al.  Structural fault collapsing by superposition of BDDs for test generation in digital circuits , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[19]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.