A memory-based architecture for very-high-throughput variable length codec design

Variable-length code/decode (VLC/VLD) is the most popular data compression technique which can reduce the storage and communication channel bandwidth needed to transmit a large amount of data. In this paper, we present a new memory-based VLSI architecture for VLC/VLD coded system. Both coding and decoding procedures are mapped onto a memory which has been minimized by using a two-bit structure. The proposed architecture mainly consists of memory and simple arithmetic unit, making it very suitable for VLSI implementation. Simulation results show that based on 0.35 /spl mu/m CMOS process, both compression rate and decompression rate up to 1.2 Gbits/s can be achieved.

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