PROBLEM TO BE SOLVED: To reduce current consumption by stopping the outputting operation of clocks when the clocks are not needed and to resume the outputting of the clocks stably when the necessity of the clocks is generated. SOLUTION: This clock synchronization circuit is provided with a delay monitor 12 delaying outputs of a clock receiver 11, a delay circuit 14 for progress pulses delaying outputs of the delay monitor, a delay circuit 16 for regression pulses delaying outputs from the receiver corresponding to the next cycle of a signal which are to be delayed at this circuit by the same delay time as that of the delay circuit 14, a driver 20 outputting internal clocks by receiving outputs of the delay circuit 16, a state holding part 18 controlling delay operations in the delay circuit 16, a control pulse generating circuit 19 initializing the delay circuit 14 and AND circuits which are provided respectively between the receiver and the delay circuit, between the delay circuit and the delay circuit 14 and between the receiver and the circuit 19.