ECC Processor with Low Die Size for RFID Applications

This paper presents the design of a special purpose processor with elliptic curve digital signature algorithm (ECDSA) functionality. This digital signature generation device (SGD) was developed especially for RFID tags. The design parameters were low energy consumption, small chip area, robustness against cryptographic attacks, and flexibility. The SGD was designed to work as digital processor in an RFID tag requiring the tag to provide the secret key storage and a PRNG. The SHA-1 calculation needs to be included into the SGD to avoid a microcontroller on the tag. The asymmetric cryptosystem allows authentication of the tag to untrusted third parties without revealing the secret key. The ECDSA functionality was implemented using a prime field GF(p) and affine coordinates, an alternative way to reduce the die size and the costs of the tag. The standard-cell based implementation of the device is fully scalable for different prime fields sizes. The GF(p192) version will need 23k gate equivalents or 1.3 mm2 for a 0.35 mum process. 502k clock cycles are used for signature generation. The near-Spice level power simulation with Nanosim estimated the final energy consumption to 0.846 mWs for a generated signature.