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Radu Mateescu | Marc Renaudin | Wendelin Serwe | Aymane Bouzafour | M. Renaudin | Radu Mateescu | Wendelin Serwe | Aymane Bouzafour
[1] Radu Mateescu,et al. CADP 2011: a toolbox for the construction and analysis of distributed processes , 2012, International Journal on Software Tools for Technology Transfer.
[2] Alain J. Martin. 25 Years Ago: The First Asynchronous Microprocessor , 2014 .
[3] Marly Roncken,et al. The VLSI-programming language Tangram and its translation into handshake circuits , 1991, Proceedings of the European Conference on Design Automation..
[4] Frédéric Lang,et al. Exp.Open 2.0: A Flexible Tool Integrating Partial Order, Compositional, and On-The-Fly Verification Methods , 2005, IFM.
[5] Marta Z. Kwiatkowska,et al. Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs , 2006, Electron. Notes Theor. Comput. Sci..
[6] Tom Verhoeff,et al. Analyzing specifications for delay-insensitive circuits , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[7] Mark B. Josephs,et al. Gate-level modelling and verification of asynchronous circuits using CSPM and FDR , 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07).
[8] Fabien Clermidy,et al. An asynchronous NOC architecture providing low latency service and its multi-level design framework , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.
[9] Marta Z. Kwiatkowska,et al. On process-algebraic verification of asynchronous circuits , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).
[10] Andrew William Roscoe,et al. The Theory and Practice of Concurrency , 1997 .
[11] Alexandre Yakovlev,et al. Modelling, analysis and synthesis of asynchronous control circuits using Petri nets , 1996, Integr..
[12] Radu Mateescu,et al. BISIMULATOR: A Modular Tool for On-the-Fly Equivalence Checking , 2005, TACAS.
[13] Luciano Lavagno,et al. On the models for asynchronous circuit behaviour with OR causality , 1996, Formal Methods Syst. Des..
[14] Frédéric Lang,et al. SVL: A Scripting Language for Compositional Verification , 2001, FORTE.
[15] C. A. R. Hoare,et al. A Theory of Communicating Sequential Processes , 1984, JACM.
[16] Doug A. Edwards,et al. Balsa: An Asynchronous Hardware Synthesis Language , 2002, Comput. J..
[17] David L. Dill,et al. Trace theory for automatic hierarchical verification of speed-independent circuits , 1989, ACM distinguished dissertations.
[18] George J. Milne,et al. An exercise in the automatic verification of asynchronous designs , 1994, Formal Methods Syst. Des..
[19] Hemangee K. Kapoor,et al. Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench , 2004, Inf. Process. Lett..
[20] Hubert Garavel,et al. The Unheralded Value of the Multiway Rendezvous: Illustration with the Production Cell Benchmark , 2017, MARS@ETAPS.
[21] Jim D. Garside,et al. SPA - a secure Amulet core for smartcard applications , 2003, Microprocess. Microsystems.
[22] Rance Cleaveland,et al. The Concurrency Workbench , 1990, Automatic Verification Methods for Finite State Systems.
[23] Alain J. Martin. Compiling communicating processes into delay-insensitive VLSI circuits , 2005, Distributed Computing.
[24] Caihong Li,et al. Modeling and Verification of Circuit with Stable-Event , 2017, 2017 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC).
[25] Frédéric Lang,et al. From LOTOS to LNT , 2017, ModelEd, TestEd, TrustEd.
[26] Ying Liu,et al. Designing parallel specifications in CCS , 1993, Proceedings of Canadian Conference on Electrical and Computer Engineering.
[27] Marc Renaudin,et al. Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits , 2018, 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).
[28] Mark B. Josephs,et al. Receptive process theory , 1992, Acta Informatica.