High Parallel VLSI Architecture Design of BPC in JPEG2000

Embedded block coding with optimized truncation (EBCOT) is the most computationally intensive part of JPEG2000 image coding standard. In order to improve the encoding efficiency, in this paper, we design a high parallel VLSI architecture of bit plane coding (BPC). Based on this proposed architecture, each encoding pass and each bit plane are encoded in parallel. Moreover, this proposed BPC can be connected with multiple MQ encoders during a coding session, which increase the encoding throughput furthermore. Logic synthesis results based on SIMC 0.25µm technology library and the throughput analysis results based on several standard test images show that the proposed architecture can work at a higher frequency and complete the encoding process with lower clock cycles compared with the available designs.