A dithering Technique for Sha_less Pipelined ADC
暂无分享,去创建一个
[1] Jonathan W. Valvano,et al. A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC , 2008, IEEE Journal of Solid-State Circuits.
[2] T. L. Sculley,et al. A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter , 2002 .
[3] A. Karanicolas,et al. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .
[4] Andrew Morgan,et al. A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration , 2010, IEEE Journal of Solid-State Circuits.
[5] M. Wagdy,et al. Linearizing average transfer characteristics of ideal ADC's via analog and digital dither , 1994 .
[6] Muhammad Taher Abuelma'atti. Harmonic and intermodulation performance of analogue-to-digital converters with multibit errors and additive dither , 2002 .
[7] M. Wagdy. Effect of various dither forms on quantization errors of ideal A/D converters , 1989 .
[8] I. Mehr,et al. A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 2000 .
[9] J. Kornblum,et al. A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter , 2006, IEEE Journal of Solid-State Circuits.