Investigation of Threshold Voltage Variability at High Temperature Using Takeuchi Plot

The property of metal–oxide–semiconductor field-effect transistors' (MOSFETs) threshold voltage (VT) variability at high temperature is investigated by evaluating the device matrix array test element group (DMA-TEG). It is revealed that VT variation is lower at high temperature than at room temperature, and that VT at high temperature has a strong correlation with VT at room temperature. The normal property of VT variability both at room and high temperatures is validated using the normal probability plot. The decrease in VT variation at high temperature stems from the reduction of the channel depletion layer width (Wdep). The temperature dependence of VT variation is evaluated using the Takeuchi plot, the VT variation normalization method. It is revealed that the change in BVT, the parameter of VT variation in the Takeuchi plot, is very small with varying temperature.