50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS

Research in recent years has shown that downscaled CMOS is a serious technology candidate to implement transceivers for high-data-rate wireless communication around 60GHz [1,2]. A low-cost implementation is the combination of the digital part with the transceiver onto a single chip. The complexity of the digital part demands a very advanced CMOS technology, such as 45nm low-power (LP) CMOS. Although this technology features a high maximum ƒT, above 200GHz, the back-end-of-line (BEOL) metallization layers are thinner than in less-advanced technology. This implies a lower quality factor for the passive components and a lower intrinsic ESD robustness due to a higher sheet resistance of the metal layers. These restrictions, together with the limited power capabilities of CMOS make the design of mm-wave power amplifiers (PAs) more challenging [3,4].

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