An Efficient Combined Bit-Flipping and Stochastic LDPC Decoder Using Improved Probability Tracers

This paper presents an efficient combined bit-flipping (BF) and stochastic low-density parity-check decoder, where a BF decoder is used to achieve a reduction in decoding cycles. A node-wise probability tracer is adopted at each variable node (VN) in order to achieve a BER performance comparable to the normalized min-sum algorithm, where check-to-variable (C2V) messages are used as inputs, rather than the variable-to-check (V2C) messages adopted in previous stochastic decoders. The complexity of the VN units is greatly reduced by sharing common units used in the generation of V2C messages together with a probability tracer. The C2V-based probability tracer enables the design of a decoder that provides a short critical path. The proposed methods are demonstrated by designing a (2048, 1723) decoder that is implemented in a 90 nm process. A total of 1460 K logic gates are integrated in a decoder that has an area of 4.12 $\mbox{mm}^2$ and achieves a coded throughput of 39.3 Gb/s at a clock frequency of 749 MHz. To the best of the authors’ knowledge, the proposed decoder achieves the best normalized throughput-to-area ratio among the stochastic decoders reported in the open literatures.