A hardware mid-value select voter architecture

This paper presents a VLSI fault-tolerant voter, with redundancy designed into the internal chip architecture. The design features are internal input interface module with built-in mechanism to detect single transmission error, and mid-value select voter logic which generates two types of output, a voted value and a congruency status level. We have performed extensive studies of error coverage design strategies of our logic for error detection and selection. Firstly, instead of three we propose installation of four sensor elements. This scheme, in the presence of single transmission error, allows the implementation of a simple replacement policy, which is based on substitution of the erroneous value (mainly a transient error), with a correct one. Secondly, in order to insure that the voted value represents a correct consensus, we propose a mid-value hardware voting technique thanks to which we solve the problem of dissemination of each sensor element value to other ones. Finally, the effect of fault-tolerance on voter performance is discussed.